Clock jitter removal in VHDL

Project: Clock jitter removal in VHDL
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Members	Danny Witberg
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Description	Jitter removal in clock signals with VHDL implementation
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Unstable clock signals

Stable clock signals in digital domains is, generally speaking, something you should aim for, and desirable in most designs. A stable clock signal is reliable, and other circuits can depend on them. For instance, a reference signal to a PLL greatly depends on its stability in order for them to generate a higher frequency with a multiple oscillation frequency.

But what is this is not the case? What if your clock signal varies in frequency? This could really ruin your day! This project describes a way to stabilize a relative low frequency signal, with a much higher frequency, but stable, reference signal. To implement this inside an FPGA, an design is proposed in VHDL.

What is jitter?

A periodic variance in the frequency of a signal is called jitter. There can be a number of other unwanted characteristics to a clock signal, but jitter is one of the most common. The higher the jitter frequency, the more problems it could cause. Preferably, the jitter frequency would be 0Hz, but if you sample a clock with a higher frequency reference clock, you always end up with some sort of jitter. The VHDL implementation of this design converts a high jitter frequency to a lower one.