ADAT project
| Project: ADAT project | |
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| State | Active |
| Members | Danny Witberg |
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| Description | This project descibes the ADAT protocol |
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1. Introduction
This project describes the Alesis© ADAT lightpipe protocol. This professional format multichannel digital audio protocol is widely used, but also closed source. Initially, it supported up to 8 channels of 24 bit digital audio at a sample frequency of 48kHz, along with a number of auxilary datastreams. At a further point, support for higher sample rates were added at the costs of the number of channels. This project describes the workings of the ADAT protocol, and proposes a possible implementation in an FPGA.
Please be advised that this project was completely reverse engineered and can only be used for educational purposes. Any results, including but not limited by, harm, pain, discomfort, death, destruction or disabling any appliance, animal or humans can not be held responsible to this project, website, page, writers or participants whatsoever. However, you are greatly encouraged to experiment, share, and learn.
2. The ADAT protocol
The ADAT lightpipe consists of an unidirectional optical connection, carrying up to 8 channels of 24 bit audio data, plus a number of auxilary data streams. The connection is divided into packets, each containing 256 bits. These packets are sent every sample point, so for an 48KHz sample rate, 48000 times a second meaning once every 20.83 microseconds. The bit rate implied by this is 12,288,000 bits per second or 12.288Mbps. This datastream is NRZI encoded for a 6.144Mbps symbol rate.
The physical interface for sending an ADAT lightpipe tream is the Toshiba TOSlink connector. This LED based connection, along with a PTFE based carrier link, can transmit ADAT up to a distance of about 10 meters and is the same that is used in an optical SP/DIF connection. However, the ADAT protocol is not backwards compatible with SP/DIF, they only share the same physical interface type.
3. Decoding ADAT
Because the data rate of 12.288Mbps is too fast for the popular TOTX173 fiber tramsit module, data is NRZI encoded by sending a '1' as a change in signal level, a '0' being sent as no change in the signal. For ensuring enough signal transitions are made, a '1' bit is sent after every 4 databits for correct decoding of the ADAT stream. This is true for almost everything about the ADAT protocol, except the synchronisation sequence. The synchronication consists of 10 '0' bits being sent, meaning a longer time that the stream stays at a defined level (being high or low level does not make a diffrence with NRZI) then anywhere else in the data signal.
With a 24 bit audio sample, this can be transmitted with this encoding scheme in 6 times a nibble-wide data chunk, each followed by a '1' bit to ensure data integrity. In all, 30 bits are used for an audio sample, and 8 of these audio samples, 240 bits out of our 256 bits are explained. Of the remaining 16, ten of those are in the synchonisation sequence, leaving 6 bits. 4 user bits can be transmitted, containing auxilary data, and this user data is encapsulated in '1' bith before and after, again for data integrity. All of the bits in the ADAT protocol are now assigned. 
4. FPGA implementation
The choice is made to make the implementation of a ADAT decoder as a feed-forward receiver. This means that, apart from the data signal itself and a high frequency unrelated clock signal, the core produces its own synchronisation and support signals for correctly decoding the stream. As a start, a frame synchronising machine is needed. The sync sequence of adat are 10 bits being '0', this means that during sync there are no transitions. This is something we can measure. Take a counter, and as long as the data signal does not change, it counts up. If the data signal changes, it resets and puts the max value is a seperate register.
Next, we need a "flag" signal that changes if there is no transition for about three quarters of the "maximum time without signal transition"-register. This means that the flag signal is active when there is a constant level for 7.5 databits or up. This is only going to happen at the sync signal, because all other times the ADAT signal is going to change after 5 bits tops. Three quarters is chosen because it is binary easy to create. Take the register, bit-shift to the left and you have only half the value left. Bit-shift to the left angain, and you'll have a quarter of the original value. Add one half to one quarter, and you'll end up with three quarters.
